On the reliability of performance counters for power models
نویسندگان
چکیده
Modern processors have been equipped with Hardware Performance Counters (HPCs) and Performance Monitoring Units (PMUs) to keep track of hardware events, building adequate tools to debug and analyze systems. Recent research projects addressed the problem of building processor power models by correlating variations on power to hardware events. Here, we intent to tease the workshop participants claiming that HPCbased power models are helpful only in very strict and controlled conditions and do not deliver reliable estimates to support power management algorithms.
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تاریخ انتشار 2013